Patch is attached to the ticket here: https://svn.boost.org/trac/boost/ticket/8593 On Thu, May 16, 2013 at 11:29 AM, Phil Endecott < spam_from_boost_dev@chezphil.org> wrote:
Having said that, I suggest always checking to see what code is actually being generated i.e. is it inline atomic instructions (ldrex & strex on ARM) or some kind of library call, even with vendor-supplied <atomic> implementations. Just look at the generated assembler for a trivial program. The fact that you're seeing a requirement to link with Boost.Atomic suggests that it is not using my inline-assembler version... explained by this post from Tim:
Below is a portion of what I get from the following simple function, I believe it indicates proper atomic support since the instructions you mention are in there. Compiling with clang / libc++ with the tools apple is shipping today (Xcode 4.6, clang 3.2), arch armv7 / armv7s: #include <atomic> void foo() { std::atomic<int> bar( 2 ); bar += 3; } /* Assembly: ... LJTI0_0_0: .data_region jt8 .byte (LBB0_5-LJTI0_0_0)/2 .byte (LBB0_5-LJTI0_0_0)/2 .byte (LBB0_8-LJTI0_0_0)/2 .byte (LBB0_11-LJTI0_0_0)/2 .byte (LBB0_14-LJTI0_0_0)/2 .end_data_region .align 1 LBB0_2: ldr r0, [sp, #96] str r0, [sp, #36] @ 4-byte Spill LBB0_3: @ =>This Inner Loop Header: Depth=1 ldr r0, [sp, #44] @ 4-byte Reload ldrex r1, [r0] ldr r2, [sp, #36] @ 4-byte Reload adds r3, r1, r2 strex r9, r3, [r0] cmp.w r9, #0 str r1, [sp, #32] @ 4-byte Spill bne LBB0_3 @ BB#4: ldr r0, [sp, #32] @ 4-byte Reload str r0, [sp, #92] b LBB0_17 LBB0_5: ldr r0, [sp, #96] str r0, [sp, #28] @ 4-byte Spill LBB0_6: @ =>This Inner Loop Header: Depth=1 ldr r0, [sp, #44] @ 4-byte Reload ldrex r1, [r0] ldr r2, [sp, #28] @ 4-byte Reload adds r3, r1, r2 strex r9, r3, [r0] cmp.w r9, #0 str r1, [sp, #24] @ 4-byte Spill bne LBB0_6 ... */